SmartSim – counters
SmartSim – Synchronous counters
In this example we’ll use SmartSim to build a Synchronous counter using JK flip flops. No not a type of shoe, but a digital circuit that has memory, able store 1 bit of information. It works in much the same way as light switch in your home. When you turn a light ON, the switch remembers to keep the light on, until you decide to turn it OFF. I.e. it has two states, ON and OFF, or in binary logic terms TRUE and FALSE. I’ll not describe the design of JK flip flop here, but suffix to say, it is the most versatile compared to other types of flip flop.
A synchronous counter is just that, a circuit element which can count. In a previous example, showing how AND, OR and NOT gates can be used to design a 4 bit adder, to add numbers up to a total of 15, a four stage synchronous counter can count from 0 – 15. In other words it has 16 possible states. Synchronous circuits are a class of circuits that only change state in synchrony with a clock. A digital computer is a type of synchronous circuit.
As with the design of a 4 bit adder we introduced the notion of truth tables, we now extend that idea, and introduce state transition diagrams. Or more simply put, how do we get from one state to the next? The answer is simple, by comparing the previous state to the current state. To help do this I’m first going to introduce one other design technique known as a Karnaugh map.
A Karnaugh map provides an alternative view of a truth table. Each cell in the table represents the corresponding row output in the truth table. The advantage of the Karnaugh map is as a visual aid to the minimisation of logic functions.
Karnaugh Map
Starting with a single variable, it can be in one of two states, either FALSE or TRUE (i.e. 0 or 1).
~A | A |
---|---|
0 | 1 |
A add a second variable, simply mirror the table above about it’s bottom horizontal) axis as shown below. We now have a table with four cells, or states.
~A | A | |
---|---|---|
~B | 0 | 1 |
B | 2 | 3 |
To add a third variable, now mirror the table about its right hand (vertical) axis. At this point you might be wondering about the way I’ve numbered the cells. I started wit variable A (the least significant bit), then added B and next C, i.e. CBA. Take cell 5 for instance, reading off the 3 axis we have A (1), NOT B (0) and C (1) or the binary number 101 which equals decimal 5.
~A | A | A | ~A | |
---|---|---|---|---|
~B | 0 | 1 | 5 | 4 |
B | 2 | 3 | 7 | 6 |
~C | ~C | C | C |
For a 4 stage counter we need one more variable, D. Again we reflect the table about the bottom (horizontal) axis. Notice we have alternated between horizontal and vertical axis. Take cell 11 for example, this is D ~C B A or binary 1001 i.e. 1 eight, no fours, no twos and 1 one, ie. decimal 11
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | 0 | 1 | 5 | 4 | ~D |
B | 2 | 3 | 7 | 6 | ~D |
B | 10 | 11 | 15 | 14 | D |
~B | 8 | 9 | 13 | 12 | D |
~C | ~C | C | C |
Synchronous Counters
The output of a sequential circuit is dependant upon both the input and the previous state of the circuit. State Transition Diagrams are used to show the progression of the circuit from one state to the next.
The general arrangement of a Synchronous sequential circuit is shown opposite.
A source of clocked pulses is gated into the circuit. Combinational logic is used to provide feedback from the previous state, so influencing the next state. In the case of a synchronous counter, clock pulses are fed in parallel to each stage of the counter.
Four stage synchronous counter
The design of a 4 stage synchronous counter is used to illustrate the design process. In this example there are no unused states.
The basic design procedure is as follows,
- Produce a state transition diagram, similar to above.
- Build a state transition table showing present state, next
state and toggle function. - From the toggle functions for each stage produce a Karnaugh
map and minimise the logic function.
State Transition table for a four stage counter
State | Present state D C B A |
Next state D C B A |
Toggle Function T_{d} T_{c} T_{b} T_{a} |
---|---|---|---|
0 | 0 0 0 0 | 0 0 0 1 | 0 0 0 1 |
1 | 0 0 0 1 | 0 0 1 0 | 0 0 1 1 |
2 | 0 0 1 0 | 0 0 1 1 | 0 0 0 1 |
3 | 0 0 1 1 | 0 1 0 0 | 0 1 1 1 |
4 | 0 1 0 0 | 0 1 0 1 | 0 0 0 1 |
5 | 0 1 0 1 | 0 1 1 0 | 0 0 1 1 |
6 | 0 1 1 0 | 0 1 1 1 | 0 0 0 1 |
7 | 0 1 1 1 | 1 0 0 0 | 1 1 1 1 |
8 | 1 0 0 0 | 1 0 0 1 | 0 0 0 1 |
9 | 1 0 0 1 | 1 0 1 0 | 0 0 1 1 |
10 | 1 0 1 0 | 1 0 1 1 | 0 0 0 1 |
11 | 1 0 1 1 | 1 1 0 0 | 0 1 1 1 |
12 | 1 1 0 0 | 1 1 0 1 | 0 0 0 1 |
13 | 1 1 0 1 | 1 1 1 0 | 0 0 1 1 |
14 | 1 1 1 0 | 1 1 1 1 | 0 0 0 1 |
15 | 1 1 1 1 | 0 0 0 0 | 1 1 1 1 |
The toggle function id determined as follows.
If the corresponding columns in the present and next states change
from,
‘0’ to ‘1’, or ‘1’ to ‘0’ enter a ‘1’ under the toggle function.
From an inspection of the table it can be seen that the toggle
function T_{a} = 1 in every state. The Karnaugh maps, below represent input state and Toggle output. Now perhaps you can see the power of a Karnaugh map, as the patterns created make clear the logic.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | 1 | 1 | ~D | ||
B | 1 | 1 | ~D | ||
B | 1 | 1 | D | ||
~B | 1 | 1 | D | ||
~C | ~C | C | C |
T_{b} = A. You should be able to see from the table that the output is true when A is true. The variables B,C and D play no part.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | ~D | ||||
B | 1 | 1 | ~D | ||
B | 1 | 1 | D | ||
~B | D | ||||
~C | ~C | C | C |
T_{c} = AB which is shorthand for A AND B. Again you can see that the output only depends on A and B. C and D have no influence.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | ~D | ||||
B | 1 | ~D | |||
B | 1 | D | |||
~B | D | ||||
~C | ~C | C | C |
T_{d} = ABC. Now the output is true only if A AND B AND C are true.
The circuit for the synchronous hexadecimal counter is shown below. The JK flip flops required for the circuit can be downloaded from the SmartSim site under examples. From the diagram you can see that the input of T_{a} is tried to logic 1. The output of T_{a} goes directly to T_{b}. The toggle function for T_{c} is A AND B, via the the AND gate. Lastly T_{d} is A AND B (from the first logic gate) and C provided by the second logic gate. By now you known how to build this circuit and run the simulation. To start the simulation make sure the T_{a} is set to 1 then click the start button. You willprobably need to show the simulation down to see what is happening.
Synchronous Decade counter
In the previous example all the logic states were used. To counter from 0 – 9 there will be unused states. This example will show how to deal with these, but otherwise follows the same procedure as above.
State | Present state D C B A |
Next state D C B A |
Toggle Function T_{d} T_{c} T_{b} T_{a} |
---|---|---|---|
0 | 0 0 0 0 | 0 0 0 1 | 0 0 0 1 |
1 | 0 0 0 1 | 0 0 1 0 | 0 0 1 1 |
2 | 0 0 1 0 | 0 0 1 1 | 0 0 0 1 |
3 | 0 0 1 1 | 0 1 0 0 | 0 1 1 1 |
4 | 0 1 0 0 | 0 1 0 1 | 0 0 0 1 |
5 | 0 1 0 1 | 0 1 1 0 | 0 0 1 1 |
6 | 0 1 1 0 | 0 1 1 1 | 0 0 0 1 |
7 | 0 1 1 1 | 1 0 0 0 | 1 1 1 1 |
8 | 1 0 0 0 | 1 0 0 1 | 0 0 0 1 |
9 | 1 0 0 1 | 0 0 0 0 | 1 0 0 1 |
This is the same as the previous state transition table down to the 8^{th} state. The 9^{th} state has changed as it must return to state 0. As before T_{a} = 1. The procedure for the other Karnaugh maps is the same as before, but now we have to take account of the unused (or don’t care states). These are indicated by an ‘x’; meaning we can make these values what we like, to suit the logic function we are trying to minimise.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | 1 | 1 | ~D | ||
B | 1 | 1 | ~D | ||
B | x | x | x | x | D |
~B | 0 | 0 | x | x | D |
~C | ~C | C | C |
T_{b} = A.~D.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | ~D | ||||
B | 1 | 1 | ~D | ||
B | x | x | x | x | D |
~B | 0 | 0 | x | x | D |
~C | ~C | C | C |
T_{c} = AB, if we make the don’t care states 11 and 15 = 1.
~A | A | A | ~A | ||
---|---|---|---|---|---|
~B | ~D | ||||
B | 1 | ~D | |||
B | x | x | x | x | D |
~B | 0 | 1 | x | x | D |
~C | ~C | C | C |
T_{d} = ABC +AD. By making the don’t care state 13 = 1.
It is at this stage though the process changes. Using these function the designer must now check what happens should the counter find itself in an unused state.
Using the functions derived above the toggle functions are determined.
State | Present state D C B A |
Next state D C B A |
Toggle Function T_{d} T_{c} T_{b} T_{a} |
---|---|---|---|
10 | 1 0 1 0 | 1 0 1 1 (11) | 0 0 0 1 |
11 | 1 0 1 1 | 0 1 1 0 ( 6) | 1 1 0 1 |
12 | 1 1 0 0 | 1 1 0 1 (13) | 0 0 0 1 |
13 | 1 1 0 1 | 0 1 0 0 ( 4) | 1 0 0 1 |
14 | 1 1 1 0 | 1 1 1 1 (15) | 0 0 0 1 |
15 | 1 1 1 1 | 0 0 1 0 ( 2) | 1 1 0 1 |
So for example, applying the toggle function present state 10,
or binary 1010 (DCBA) gives
T_{a} = 1, T_{b} = A.~D i.e. 0 AND 0 = 0, T_{c} = A.B i.e 1 AND 0 = 0, and lastly T_{d} = ABC + AD = (0 AND 1 AND 0) OR (0 AND 0) = 0 OR 0 = 0. So in the table above for state 10 the only bit which changes is A so 1010 (decimal 10) becomes 1011 (decimal 11).
This process is repeated for each of the other unused states producing the table above. Finally the state transition diagram can be completed, filling in the unused states.
Why is it important to check the unused states?. Because when the counter is initially turned on, it might start in one of these unused states. As you can now see from the diagram all unused states lead into the main sequence, so leading to the correct count.
The SmartSim implementation is shown below. The first AND gate provides the logic function A AND NOT D. The NOT D being taken from the NOT Q output of the Td flip flip.
As well as the circuit simulation, you can attach the watch (or tracer) to various inputs to generate a timing diagram. This is shown below.
Summary
For anyone interested in digital electronics, SmartSim is a very useful tool, and as these tutorials have shown, its performed well with these moderately complex circuits. The tutorials have also briefly touched on some the techniques employed in digital design. The ability to step through the different circuit states is a very useful aid to diagnostics, as is the changing colours of the wires, denoting different signal levels.
Some care must be taken when connecting up components and its recommended you magnify the area you are working on, to ensure connections are made properly, otherwise this can be rather fiddly process. Do not make connections to close to the component pins, as this to can be a potential source of error. Even though a circuit passes the validation test, that does not necessarily mean its wired up as intended.
When building up complex circuits, start a new folder to keep all the sub components together. Something you probably need to do anyway if you intend to share your designs.